Static Timing Analysis for Nanometer Designs

Name: Static Timing Analysis for Nanometer Designs
Brand: Springer-Verlag New York Inc.
SKU: 9780387938196
Price: 1031.86 PLN
Availability: InStock

A Practical Approach

Autor: J. Bhasker, Rakesh Chadha

Język:

Oprawa: Twarda

Wydawca: Springer-Verlag New York Inc.

Dostępność: Dostępna u dostawcy

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The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, d...

Informacje o książce

Autor

J. Bhasker, Rakesh Chadha

Język

Angielski

Oprawa

Książka - Twarda

Data wydania

2009

strony

572

EAN

9780387938196

ISBN

0387938192

Enbook ID

01383926

Wydawca

Springer-Verlag New York Inc.

Waga

2210

Wymiary

155 x 235 x 40

Pełny opis

The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts.§The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology.§This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for analysis of internal paths as well as IO interfaces. Advanced modeling and analysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces are also covered.

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Static Timing Analysis for Nanometer Designs

A Practical Approach

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