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Książka Nanoscale Strain-engineering in Solid State Semiconductor Devices Sulagna Chatterjee

Nanoscale Strain-engineering in Solid State Semiconductor Devices

Autor: Sulagna Chatterjee
Język: Angielski
Oprawa: Miękka
Wydawca: KS OmniScriptum Publishing
Dostępność: Dostępna u dostawcy
Wysyłamy za 8-11 dni
252.96 zł
An analytical model has been developed that estimates induced stress in horizontally embedded nanowi...

Informacje o książce

Autor
Sulagna Chatterjee
Język
Angielski
Oprawa
Książka - Miękka
Data wydania
2026
strony
136
EAN
9786209522390
ISBN
6209522394
Enbook ID
51525201
Wydawca
KS OmniScriptum Publishing
Waga
193
Wymiary
152 x 229 x 8

Pełny opis

An analytical model has been developed that estimates induced stress in horizontally embedded nanowires. Stress has been considered to be induced due to mismatch of both lattice and thermo-elastic constants. The contribution of both process- and substrate-induced stress has been accounted for. Various materials have been chosen as substrate for different nanowire materials, depending on their crystal structures. The magnitude and nature of induced stress has been engineered by varying the fractional insertion of the nanowire into the substrate. Nanowires being extremely petite structures always need to be mounted on some substrate. Hence, a commercial substrate has been proposed, such that mobility enhancement through stress-engineering might be accomplished by varying the fractional insertion. Step-by-step stress-engineering for partially embedded nanowire FETs has been performed. The choice of high-k gate dielectric has been shown to play an important role. Similar stress-engineering has been performed for UTB MOSFETs and FinFETs. Both such FETs have been proposed to be fabricated on ingenious, commercial IOS substrates, capable of inducing stress of desired nature and magnitude.