Morphological Image Processing: Architecture and VLSI design

Name: Morphological Image Processing: Architecture and VLSI design
Brand: Kluwer Academic Publishers Group
SKU: 9789020127669
Price: 635.01 PLN
Availability: InStock

Autor: P. P. Jonker

Język:

Oprawa: Miękka

Wydawca: Kluwer Academic Publishers Group

Dostępność: Dostępna u dostawcy

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This book describes image processing research based on the morphology of the objects in an image and...

Informacje o książce

Autor

P. P. Jonker

Język

Angielski

Oprawa

Książka - Miękka

Data wydania

1993

strony

297

EAN

9789020127669

ISBN

9020127667

Enbook ID

01968322

Wydawca

Kluwer Academic Publishers Group

Waga

960

Wymiary

160 x 240 x 17

Pełny opis

This book describes image processing research based on the morphology of the objects in an image and a VLSI design of a Cellular Logic Processing Element for a real-time processor pipeline. The field of image processing has spawned a number of special parallel computer architectures: the Square (SIMD), Processor Array, the Pyramid, the Linear Processor Array (or scan line array) and the Processor Pipeline. This book features a classification of low-level image processing operations, reviews some intermediate level algorithms, and gives a short introduction into computer architecture used for image and digital signal processing. Morphology-based processing images is introduced by treating cellular logic operations such as skeletonization as hit-or-miss transformations. This approach can be extended to images of higher dimensions than two and a method is described to construct hit-or-miss masks for the skeletonization of these images. In the second part of the book a study is performed on the speed bottlenecks that can be found in the main architectural groups followed by the description of a method for the structured design of integrated, digital hardware. The VLSI design of a CMOS Processing Element for the real-time processing of binary images and the board level design of a scalable processor pipeline for a real-time low-level processing of grey value images is described in detail. Finally, a computer architecture for low and intermediate processing of two and three dimensional images if proposed.

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