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Książka IMPLEMENTATION OF HIGH PERFORMANCE 32-BIT RISC CORE ARCHITECTURE M. Rajani

IMPLEMENTATION OF HIGH PERFORMANCE 32-BIT RISC CORE ARCHITECTURE

Autor: M. Rajani, D. Ravi Chandan
Język: Angielski
Oprawa: Miękka
Wydawca: LAP LAMBERT Academic Publishing
Dostępność: Dostępna u dostawcy
Wysyłamy za 8-11 dni
164.38 zł
This book is about designing a RISC processor using pipelined architecture. 5-stage pipelining is us...

Informacje o książce

Autor
M. Rajani, D. Ravi Chandan
Język
Angielski
Oprawa
Książka - Miękka
Data wydania
2023
strony
84
EAN
9786206183303
ISBN
6206183300
Enbook ID
43770256
Wydawca
LAP LAMBERT Academic Publishing
Waga
143
Wymiary
150 x 220 x 6

Pełny opis

This book is about designing a RISC processor using pipelined architecture. 5-stage pipelining is used to improve the speed of the operation. The 5 stages are Fetch, Decode, Execute, Memory and Write Back. The design process includes various low power techniques at architectural level which proves that this methods is more efficient than Back-end low power reduction techniques. Low power embedded processors are used in a wide variety of applications including cars, phones, digital cameras, printers, and other such devices. The reason for their wide use is that they are small therefore, they do not take up much die area and are cost effective to fabricate. Low power consumption helps to reduce the heat dissipation, lengthen battery life and increase device reliability.

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