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Fast, Efficient and Predictable Memory Accesses

Name: Fast, Efficient and Predictable Memory Accesses
Brand: Springer
SKU: 9789048172009
Price: 422.9 PLN
Availability: InStock

Optimization Algorithms for Memory Architecture Aware Compilation

Autor: Lars Wehmeyer, Peter Marwedel

Język:

Oprawa: Miękka

Wydawca: Springer

Dostępność: Dostępna u dostawcy

Wysyłamy za 5-8 dni

422.90 zł

Speed improvements in memory systems have not kept pace with the speed improvements of processors, l...

Informacje o książce

Autor

Lars Wehmeyer, Peter Marwedel

Język

Angielski

Oprawa

Książka - Miękka

Data wydania

2010

strony

258

EAN

9789048172009

ISBN

9048172004

Enbook ID

01975394

Wydawca

Springer

Waga

440

Wymiary

160 x 240 x 15

Pełny opis

Speed improvements in memory systems have not kept pace with the speed improvements of processors, leading to embedded systems whose performance is limited by the memory. This book presents design techniques for fast, energy-efficient and timing-predictable memory systems that achieve high performance and low energy consumption. In addition, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds.The memory system is increasingly turning into a bottleneck in the design of embedded systems. The speed improvements of memory systems are lower than the speed improvements of processors, eventually leading to embedded systems whose performance is limited by the memory. This problem is known as the "memory wall" problem. Furthermore, memory systems may consume the largest share of the system s energy budget and may be the source of unpredictable timing behaviour. Hence, the design of the memory system deserves an increasing amount of attention. §Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.