Angielski
Deep learning models deployed on Edge devices, such as mobile phones and IoT terminals, generally use Cloud computing, presenting a range of concerns around privacy, latency and power consumption. In turn, Edge computing enables inference operations, and even training progress, to be completed on embedded devices themselves, rather than in the Cloud. With on-device deep learning, reliability becomes independent of network availability or bandwidth, data processing becomes much faster, and the problems associated with the Cloud are eliminated. Deep Learning on Edge Computing Devices focuses on hardware architecture and embedded deep learning, including neural networks. The title helps researchers maximize the performance of Edge-deep learning models for mobile computing and other applications, by presenting neural network algorithms and hardware design optimization approaches for Edge-deep learning. Applications are introduced in each section, and a comprehensive example, smart surveillance cameras, is presented at the end of the book, integrating innovation in both algorithm and hardware architecture. This book presents a summary of technology around Edge-deep learning. Structured into three parts, the first introduces core concepts; the second presents theories and algorithms; and part three details architecture optimization. This book provides a solution for researchers looking to maximize the performance of deep learning models on Edge-computing devices, through algorithm-hardware co-design. Focuses on hardware architecture and embedded deep learning, including neural networks Brings together neural network algorithm and hardware design optimization approaches to deep learning, alongside real-world applications Considers how Edge computing solves privacy, latency, and power consumption concerns related to the use of the Cloud Describes how to maximize the performance of deep learning on Edge-computing devices Presents the latest research on neural network compression coding, deep learning algorithms, chip co-design, and intelligent monitoring
